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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11144-1E
MEMORY
Un-buffered
4 M x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM MB8504S064CE-100/-100L
144-pin, 2 Clock, 1-bank, based on 4 M x 16 Bit SDRAMs with SPD s DESCRIPTION
The Fujitsu MB8504S064CE is a fully decoded, CMOS Synchronous Dynamic Random Access Memory (SDRAM) Module consisting of four MB81F641642C devices which organized as two banks of 4 M x 16 bits and a 2K-bit serial EEPROM on a 144-pin glass-epoxy substrate. The MB8504S064CE features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB8504S064CE is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations. This module is ideally suited for workstations, PCs, laser printers, and other applications where a simple interface is needed.
s PRODUCT LINE & FEATURES
Parameter Clock Frequency Burst Mode Cycle Time Access Time from Clock Operating Current Power Down Mode Current (ICC2P) Self Refresh Current (ICC6) 8 mA max. 4 mA max. * * * * MB8504S064CE -100 100 MHz max. 10 ns min. 8.5 ns max. (CL = 3) 360 mA max. 4 mA max. 2 mA max. -100L
* Unbuffered 144-pin SO-DIMM Socket Type (Lead pitch: 0.8 mm) * Conformed to JEDEC Standard (2 CLK) * Organization: 4,194,304 words x 64 bits * Memory: MB81F641642C (4 M x 16, 4-bank) x 4 pcs. * 3.3 V 0.3 V Supply Voltage * All input/output LVTTL compatible * 4096 Refresh Cycle every 65.6 ms
Auto and Self Refresh CKE Power Down Mode DQM Byte Masking (Read/Write) Serial Presence Detect (SPD) with Serial EEPROM: JEDEC Standard SPD Format * Module size: 1.0" (height) x 2.66" (length) x 0.15" (thickness) * CL-tRCD-tRP: 3-3-3 clk min. @100 MHz, 2-2-2 clk min. @66 MHz
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MB8504S064CE-100/-100L
s PACKAGE
144-pin plastic DIMM (socket type)
(MDS-144P-P08)
Package and Ordering Information
- 144-pin SO-DIMM, order as MB8504S064CE-100DG (DG = Std. power ver., Gold Pad) -100LDG (LDG = Low power ver., Gold Pad)
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MB8504S064CE-100/-100L
s PIN ASSIGNMENTS
Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 Signal Name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 Pin No. 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 Signal Name DQ13 DQ14 DQ15 VSS N.C. N.C. CLK0 VCC RAS WE CS0 N.C. N.C. VSS N.C. N.C. VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 Pin No. 97 99 Signal Name DQ22 DQ23 Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 Signal Name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 Pin No. 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 Signal Name DQ45 DQ46 DQ47 VSS N.C. N.C. CKE0 VCC CAS N.C. N.C. N.C. CLK1 VSS N.C. N.C. VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 Pin No. 98 Signal Name DQ54
100 DQ55 102 VCC 104 A7 106 BA0 108 VSS 110 BA1 112 A11 114 VCC 116 DQMB6 118 DQMB7 120 VSS 122 DQ56 124 DQ57 126 DQ58 128 DQ59 130 VCC 132 DQ60 134 DQ61 136 DQ62 138 DQ63 140 VSS 142 SCL 144 VCC
101 VCC 103 A6 105 A8 107 VSS 109 A9 111 A10 113 VCC 115 DQMB2 117 DQMB3 119 VSS 121 DQ24 123 DQ25 125 DQ26 127 DQ27 129 VCC 131 DQ28 133 DQ29 135 DQ30 137 DQ31 139 VSS 141 SDA 143 VCC
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MB8504S064CE-100/-100L
TOP VIEW
67.60 mm PLANE 0 Chip 0 Chip 2
25.40 mm 1
59
61
143
2 Chip 1
60
62 Chip 3
144
PLANE 1
(MDS-144P-P08)
s PIN DESCRIPTIONS
Symbol A0 to A11 BA0, BA1 RAS CAS WE DQMB0 to DQMB7 CLK0, CLK1 CKE0 I/O I I I I I I I I Function Address Input Bank Address Row Address Strobe Column Address Strobe Write Enable Data (DQ) Mask Clock Input Clock Enable Symbol CS0 DQ0 to DQ63 VCC VSS N.C. SCL SDA I/O I -- -- -- I I/O Function Chip Select Power Supply (+3.3 V) Ground (0 V) No Connection Serial PD Clock Serial PD Address/Data Input/Output
I/O Data Input/Data Output
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MB8504S064CE-100/-100L
s SERIAL-PD INFORMATION
Byte Function Described Hex Value
-100/100L
Defines Number of Bytes Written into Serial Memory at Module Manufacture Total Number of Bytes of SPD Memory Device 1 2 Fundamental Memory Type Number of Row Addresses 3 Number of Column Addresses 4 Number of Module Banks 5 6 Data Width 7 Data Width (Continuation) Interface Type 8 9 SDRAM Cycle Time (Highest CAS Latency) SDRAM Access from Clock (Highest CAS Latency) 10 DIMM Configuration Type 11 Refresh Rate/Type 12 Primary SDRAM Width 13 Error Checking SDRAM Width 14 Minimum Clock Delay for Back to Back Random Column 15 Addresses Burst Lengths Supported 16 17 Number of Banks on Each SDRAM Device 18 CAS Latency CS Latency 19 Write Latency 20 SDRAM Module Attributes 21 SDRAM Device Attributes 22 SDRAM Cycle Time (2nd. Highest CAS Latency) 23 SDRAM Access from Clock (2nd. Highest CAS Latency) 24 SDRAM Cycle Time (3rd. Highest CAS Latency) 25 SDRAM Access from Clock (3rd. Highest CAS Latency) 26 Precharge to Activate Min. (tRP) 27 28 Row Activate to Row Activate Min. (tRRD) 29 RAS to CAS Delay Min. (tRCD) 30 Activate to Precharge Minimum Time (tRAS) 31 Module Bank Density 32 to 61 Unused Storage Locations 62 SPD Data Revision Code 63 Checksum for Byte 0 to 62 64 to 98 Manufacturer's Information: Unused Storage 99 to 125 Vendor Specific Data: Unused Storage 126 Intel Specification Frequency 127 Intel Specification Details for 66 MHZ Support Unused Storage Locations 128+ 0
128 Byte 256 Byte SDRAM 12 8 1 bank 64 bit +0 LVTTL 10 ns 8.5 ns Non-Parity Self, Normal x16 0 1 Cycle 1, 2, 4, 8, Page 4 bank 2, 3 0 0 UN-buffer *1 15 ns 9 ns No Support No Support 30 ns 20 ns 30 ns 60 ns 32 MByte -- 1 *2 -- -- 66 MHZ CL=2, 3 --
80h 08h 04h 0Ch 08h 01h 40h 00h 01h A0h 85h 00h 80h 10h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh F0h 90h 00h 00h 1Eh 14h 1Eh 3Ch 08h 00h 01h 56h 00h 00h 66h 8Fh --
Note: Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127. Some or all data stored into Byte 0 to Byte 127 may be broken. *1. SDRAM Device Attributes
Bit7 TBD 0 Bit6 TBD 0 Bit5 Upper VCC tolerance 0 = 10% 0 Bit4 Lower VCC tolerance 0 = 10% 0 Bit3 Supports Write 1/ Read Burst 1 Bit2 Supports Precharge All 1 Bit1 Supports AutoPrecharge 1 Bit0 Supports Early RAS Precharge 0
*2. Checksum for Bytes 0 to 62 This byte is the checksum for bytes 0 through 62. This byte contains the value of the low 8-bits of the arithmetic sum of bytes 0 through 62. 5
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MB8504S064CE-100/-100L
s BLOCK DIAGRAM
A0 to A11, BA0, BA1 RAS CAS WE Add. RAS CAS WE DQMU 4 M x 16 Chip 0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB5 Add. RAS CAS WE DQML 4 M x 16 Chip 1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQMB0 DQMB1
DQML
DQMU
10 CLK0 10
CKE CS CLK
CKE CS CLK
Add. RAS CAS WE DQMU DQMB2 DQMB3
CLK
4 M x 16 Chip 2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7
Add. RAS CAS WE DQML
CLK
4 M x 16 Chip 3
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQML
DQMU
CKE CS CKE0 CS0
CKE CS
10 CLK1 10 pF
SERIAL EEPROM SCL SCL A0 A1 SDA A2 SDA
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MB8504S064CE-100/-100L
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Supply Voltage* Input Voltage* Output Voltage* Storage Temperature Power Dissipation Output Current (D.C.) * : Voltages referenced to VSS (= 0 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VCC VIN VOUT TSTG PD IOUT Value Min. -0.5 -0.5 -0.5 -55 -- -50 Max. +4.6 +4.6 +4.6 +125 4.0 +50 Unit V V V C W mA
s RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage, All Inputs Input Low Voltage, All Inputs Ambient Temperature *1. Voltages referenced to VSS (= 0 V)
4.6 V 50% of pulse amplitude VIH VIHmin VIL Pulse width 5 ns VIH VILmax VIL 50% of pulse amplitude Pulse width 5 ns
Notes *1 *1, 2 *1, 3
Symbol VCC VSS VIH VIL TA
Value Min. 3.0 0 2.0 -0.5 0 Typ. 3.3 0 -- -- -- Max. 3.6 0 VCC +0.5 0.8 +70
Unit V V V V C
*2. Overshoot limit: VIH (max) = 4.6 V for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude.
-1.5V *3. Undershoot limit: VIL (min) = VSS -1.5 V for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB8504S064CE-100/-100L
s CAPACITANCE
(VCC = +3.3 V, f = 1 MHz, TA = +25C) Parameter A0 to A11, BA0, BA1 RAS, CAS, WE CS0 Input Capacitance CKE0 CLK0, CLK1 DQMB0 to DQMB7 SCL Input/Output Capacitance SDA DQ0 to DQ63 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CSCL CSDA CDQ Value Min. -- -- -- -- -- -- -- -- -- Max. 34 33 29 28 34 13 7 7 13 Unit pF pF pF pF pF pF pF pF pF
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MB8504S064CE-100/-100L
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 1, 2
Value Parameter Notes Symbol Condition Burst: Length = 1 tRC = min for BL = 1 tCK = min One Bank Active, Outputs Open Addresses changed up to 1-time during tCK (min.) 0 V VIN VIL (max.) VIH (min.) VIN VCC CKE = VIL, All Banks Idle tCK = min, Power Down Mode 0 V VIN VIL (max.) VIH (min.) VIN VCC CKE = VIL, All Banks Idle CLK = H or L, Power Down Mode 0 V VIN VIL (max.) VIH (min.) VIN VCC CKE = VIH, All Banks Idle, tCK = min NOP commands only, Input signals (except to CMD) are changed 1-time during 3 clock cycles 0 V VIN VIL (max.) VIH (min.) VIN VCC CKE = VIH, All Banks Idle CLK = H or L, Input signal are stable 0 V VIN VIL (max.) VIH (min.) VIN VCC CKE = VIL, Any Bank Active tCK = min. 0 V VIN VIL (max.) VIH (min.) VIN VCC CKE = VIL, Any Bank Active CLK = H or L 0 V VIN VIL (max.) VIH (min.) VIN VCC CKE = VIH, Any Bank Active tCK = min., NOP commands only, Input signals (except to CMD) are changed 1-time during 3 clock cycles 0 V VIN VIL (max.) VIH (min.) VIN VCC CKE = VIH, Any Bank Active CLK = H or L 0 V VIN VIL (max.) VIH (min.) VIN VCC Min. Max.
Std. ver. Low ver.
Unit
Operating Current (Average Power Supply Current)
*3
ICC1S
--
360
mA
ICC2P
--
8
4
mA
ICC2PS Precharge Standby Current (Power Supply Current)
--
4
2
mA
*3 ICC2N
--
40
mA
ICC2NS
--
8
mA
ICC3P
--
8
4
mA
ICC3PS Active Standby Current (Power Supply Current)
--
4
2
mA
*3 ICC3N
--
60
mA
ICC3NS
--
8
mA
(Continued)
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MB8504S064CE-100/-100L
(Continued)
Value Parameter Notes Symbol Condition tCK = min, Burst Length = 4 Outputs Open, All Banks Active Gapless Data 0 V VIN VIL (max.) VIH (min.) VIN VCC Auto Refresh tCK = min tRC = min 0 V VIN VIL (max.) VIH (min.) VIN VCC Self-Refresh tCK = min. CKE 0.2 V 0 V VIN VIL (max.) VIH (min.) VIN VCC 0 V VIN VCC All other pins not under test = 0 V 0 V VIN VCC Output is disabled (Hi-Z) IOH = -2.0 mA IOL = +2.0 mA Min. Max.
Std. ver. Low ver.
Unit
Burst Mode Current (Average Power Supply Current)
*3
ICC4
--
340
mA
Auto-refresh Current (Average Power Supply Current)
*3
ICC5
--
680
mA
Self-refresh Current (Average Power Supply Current) Input Leakage Current (All Inputs) Output Leakage Current LVTTL Output High Voltage LVTTL Output Low Voltage
*3
ICC6
--
4
2
mA
II (L) IO (L) *4 *4 VOH VOL
-20 -5 2.4 --
20 5 -- 0.4
A A V V
Notes: *1. An initial pause (DESL on NOP) of 200 s is required after power-on followed by a minimum of eight Auto-refresh cycles. *2. DC characteristics is the Serial PD standby state (VIN = VSS or VCC). *3. ICC depends on the output termination, load conditions, clock cycle rate and signal clock rate. The specified values are obtained with the output open and no termination register. *4. Voltages referenced to VSS = VSSQ (= 0 V)
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MB8504S064CE-100/-100L
s AC CHARACTERISTICS
(1) BASE CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 1, 2, 3
No. Parameter Notes CL = 3 CL = 2 Symbol tCK3 tCK2 tCH tCL tSI tHI *4, *5 *6 *6 *6 CL = 3 CL = 2 CL = 3 CL = 2 tAC3 tAC2 tLZ tHZ3 tHZ2 tOH tREF tT tCKSP MB8504S064CE -100/100L Min. 1 2 3 4 5 6 7 8 9 10 11 12 Clock Period Clock High Time Clock Low Time Input Setup Time Input Hold Time Output Valid from Clock (tCLK = min) Output in Low-Z Output in High-Z Output Hold Time Time between Refresh Transition Time CKE Setup Time for Power Down Exit Time 10 15 3.5 3.5 3 1 -- -- 0 3 3 3 -- 0.5 3 Max. -- -- -- -- -- -- 8.5 9 -- 8.5 9 -- 65.6 2 -- ns ns ns ns ns ns ns ns ns ns ns ms ns ns Unit
(2) BASE VALUES FOR CLOCK COUNT/LATENCY
No. 1 2 3 4 5 6 7 8 9 Parameter RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time RAS to CAS Bank Active Delay Time Data-in to Precharge Lead Time Data-in to Active/Refresh Command Period Mode Register Set Cycle Time CL = 3 CL = 2 *8 Notes *7 Symbol tRC tRP tRAS tRCD tWR tRRD tDPL tDAL3 tDAL2 tRSC MB8504S064CE -100/100L Min. 90 30 60 30 10 20 10 2 cyc + tRP 1 cyc + tRP 20 Max. -- -- 110000 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns Unit
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MB8504S064CE-100/-100L
(3) CLOCK COUNT FORMULA (*9)
Clock Base Value Clock Period (Round off a whole number)
(4) LATENCY (The latency values on these parameters are fixed regardless of clock period.)
No. 1 2 3 4 5 6 7 8 9 CKE to Clock Disable DQM to Output in High-Z DQM to Input Data Delay Last Output to Write Command Delay Write Command to Input Data Delay Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay CAS to CAS Delay (min) CAS Bank Delay (min) CL = 3 CL = 2 CL = 3 CL = 2 Parameter Symbol ICKE IDQZ IDQD IOWD IDWD IROH3 IROH2 IBSH3 IBSH2 ICCD ICBD MB8504S064CE -100/100L 1 2 0 2 0 3 2 3 2 1 1 Unit Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle
Notes: *1. An initial pause (DESL on NOP) of 200 s is required after power-up followed by a minimum of eight Auto-refresh cycles. *2. 1.4 V or VREF is the reference level for measuring timing of signals. Transition times are measured between VIH (min) and VIL (max). *3. AC characteristics assume tT = 1 ns and 50 pF of capacitive load. *4. Maximum value of CL = 2 depends on tCK. *5. tAC also specifies the access time at burst mode except for first access. *6. Specified where output buffer is no longer driven. tOH, tLZ, and tHZ define the times at which the output level achieves 200 mV. *7. Actual clock count of tRC (IRC) will be sum of clock count of tRAS (IRAS) and tRP (IRP). *8. Operation within the tRCD (min) ensures that access time is determined by tRCD (min) + tAC (max); if tRCD is greater than the specified tRCD (min), access time is determined by tCAC and tAC. *9. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *Source: See MB81F641642C Data Sheet for details on the electrical.
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MB8504S064CE-100/-100L
s AC OPERATING TEST CONDITION (Example of AC Test Load Circuit)
1.4 V
50
Z = 50 I/O
50 pF
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MB8504S064CE-100/-100L
s SERIAL PRESENCE DETECT(SPD) FUNCTION
1. PIN DESCRIPTIONS
SCL (Serial Clock) SCL input is used to clock all data input/output of SPD SDA (Serial Data) SDA is a common pin used for all data input/output of SPD. The SDA pull-up resistor is required due to the open-drain output. SA0, SA1, SA2 (Address) Address inputs are used to set the least significant three bits of the eight bits slave address. The address inputs must be fixed to select a particular module and the fixed address of each module must be different each other. For this module, any address inputs are not required because all addresses (SA0, SA1, SA2) are driven to VSS on the module.
2. SPD OPERATIONS
CLOCK and DATA CONVENTION Data states on the SDA can change only during SCL = Low. SDA state changes during SCL = High are indicated start and stop conditions. Refer to Fig. 1 below. START CONDITION All commands are preceded by a start condition, which is a transition of SDA state from High to Low when SCL = High. SPD will not respond to any command until this condition has been met. STOP CONDITION All read or write operation must be terminated by a stop condition, which is a transition of SDA state from Low to High when SCL = High. The stop condition is also used to make the SPD into the state of standby power mode after a read sequence.
Fig. 1 - START AND STOP CONDITIONS
SCL
SDA
START START = High to Low transition of SDA state when SCL is High STOP = Low to High transition of SDA state when SCL is High
STOP
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MB8504S064CE-100/-100L
ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will put the SDA line to Low in order to acknowledge that it received the eight bits of data. The SPD will respond with an acknowledge when it received the start condition followed by slave address issued by master. In the read operation, the SPD will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is issued by master, the SPD will continue to transmit data. If an acknowledge is not detected, the SPD will terminated further data transmissions. The master must then issue a stop condition to return the SPD to the standby power mode. In the write operation, upon receipt of eight bits of data the SPD will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. SLAVE ADDRESS ADDRESSING Following a start condition, the master must output the eight bits slave address. The most significant four bits of the slave address are device type identifier. For the SPD this is fixed as 1010[B]. Refer to the Fig. 2 below. The next three significant bits are used to select a particular device. A system could have up to eight SPD devices --namely up to eight modules-- on the bus. The eight addresses for eight SPD devices are defined by the state of the SA0, SA1 and SA2 inputs. For this module, the three bits are fixed as 000[B] because all addresses are driven to VSS on the module. Therefore, no address inputs are required. The last bit of the slave address defines the operation to be performed. When R/W bit is "1", a read operation is selected, when R/W bit is "0", a write operation is selected. Following the start condition, the SPD monitors the SDA line comparing the slave address being transmitted with its slave address (device type and state of SA0, SA1, and SA2 inputs). Upon a correct compare the SPD outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the SPD will execute a read or write operation. Fig. 2 - SLAVE ADDRESS
DEVICE TYPE IDENTIFIER DEVICE ADDRESS
1
0
1
0
SA2
SA1
SA0
R/W
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MB8504S064CE-100/-100L
3. READ OPERATIONS
CURRENT ADDRESS READ Internally the SPD contains an address counter that maintains the address of the last data accessed, incremented by one. Therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). Upon receipt of the slave address with the R/W bit = "1", the SPD issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 3 for the sequence of address, acknowledge and data transfer.
Fig. 3 - CURRENT ADDRESS READ
S T A R T SLAVE ADDRESS S T O P
BUS ACTIVITY : MASTER SDA LINE BUS ACTIVITY : SPD
A C K
DATA
RANDOM READ Random Read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit = "1", the master must first perform a "dummy" write operation on the SPD. The master issues the start condition, and the slave address followed by the word address. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/ W bit = "1". This will be followed by an acknowledge from the SPD and then by the eight bits of data. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 4 for the sequence of address, acknowledge and data transfer.
Fig. 4 - RANDOM READ
S T A R T S T A R T
BUS ACTIVITY : MASTER SDA LINE BUS ACTIVITY : SPD
SLAVE ADDRESS
WORD ADDRESS
SLAVE ADDRESS
S T O P
A C K
A C K
A C K
DATA
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MB8504S064CE-100/-100L
SEQUENTIAL READ Sequential Read can be initiated as either a current address read or random read. The first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. The SPD continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 5 for the sequence of address, acknowledge and data transfer. The data output is sequential, with the data from address(n) followed by the data from address(n+1). The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter "rolls over" to address0 and the SPD continues to output data for each acknowledge received.
Fig. 5 - SEQUENTIAL READ
SLAVE ADDRESS BUS ACTIVITY : MASTER SDA LINE BUS ACTIVITY : SPD A C K A C K A C K A C K S T O P
DATA (n)
DATA (n+1)
DATA (n+2)
DATA (n+x)
4. DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current Output Low Voltage Note: *1. Referenced to VSS. *1 Note Symbol SILI SILO SVOL Condition 0 V VIN VCC 0 V VOUT VCC IOL = 3.0 mA Value Min. -10 -10 -- Max. 10 10 0.4 Unit A A V
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MB8504S064CE-100/-100L
5. AC CHARACTERISTICS
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Parameter SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time Symbol fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR Value Min. -- -- -- 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 100 -- Max. 100 100 3.5 -- -- -- -- -- -- -- 1 300 -- -- 15 Unit
KHz
ns s s s s s s s ns s ns s ns ms
Fig. 6 - TIMING WAVEFORM
tF tHIGH tLOW SCL tSU : STA tHD : DAT tHD : STA SDA (input) tAA SDA (output) tDH tSU : DAT tSU : STO tR
tBUF
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MB8504S064CE-100/-100L
s PACKAGE DIMENSION
144-pin plastic DIMM (socket type) (MDS-144P-P08)
2.100.10 (.083.004) 67.600.13(2.661.005) 3.80(.150)MAX 4.000.10 (.157.004)
25.400.13 (1.000.005) "A"
1
Details of "A" part 20.000.10 (.787.004) "B"
143
2.500.10 (.098.004) NOTCHES FULL R 4.000.10 (.157.004) 1.500.10 (.059.004) 4.600.13 (.181.005)
3.300.13 (.130.005) Pin No.1 INDEX
23.200.05 (.913.002) 24.50(.965)TYP 29.000.10(1.142.004)
32.800.05 (1.291.002)
4.00(.157)MIN
63.600.10(2.504.004)
1.000.10 (.039.004)
3.700.13 (.146.005) 6.000.08 (.236.003)
2
23.200.05 (.913.002) 2.100.10 (.083.004)
32.800.05 (1.291.002) 4.600.13 0.800.03 (.181.005) (.031.001)
144
Details of "B" part 0.600.05 (.024.002)
O1.800.05 (O.071.002) NOTCHES FULL R
0.25(.010)MAX
2.55(.100)MIN
C
1997 FUJITSU LIMITED M144008SC-2-2
Dimension in mm (inches).
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MB8504S064CE-100/-100L
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9812 (c) FUJITSU LIMITED Printed in Japan
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